Tim 'mithro' Ansell

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Tim 'mithro' Ansell

Tim 'mithro' Ansell

@mithro

Open Source Hardware Geek

Sydney, Australia Katılım Ocak 2009
598 Takip Edilen6.3K Takipçiler
Tim 'mithro' Ansell retweetledi
GwenhaelGoavec
GwenhaelGoavec@GwenhaelG·
Another milestone with the @Terasic_FPGA Atum A3-Nano(@AlteraFPGA_ Agilex 3): this time running @enjoy_digital LiteX! ✅ SDRAM ✅ SD card ✅ HDMI ✅ Ethernet via the new Agilex RGMII PHY Linux-on-LiteX-VexRiscv integration is done too: SD boot, serial boot, and TFTP! #LiteX #FPGA #Linux
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Runtime
Runtime@RuntimeBRT·
Indian students are DIYing a semiconductor fab at IIT Bombay. In just 10 months they've built: 1. A DLP-based lithography machine. 2. A tube furnace to oxidise silicon. 3. A DC plasma sputter. Total cost: ₹30 lakh. Here's a rare behind-the-scenes look at HackerFab IITB.
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b a b a@mesnavi·
@mithro I bought 2 #fomu fpga from @MouserElec and one of them is not working. The touch buttons are not working. The copper is missing. As you can see in the pictures. Any help!!
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Rahul Bhagwat
Rahul Bhagwat@RahulBhagwat01·
hyped for this! Thanks everyone at @tinytapeout for the support and @mithro for making this happen!
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gojimmypi
gojimmypi@gojimmypi·
My latest gizmo arrived today!! This is the @tinytapeout FPGA development kit. It has a Lattice #UP5K FPGA on a PCB with headers and a pinout compatible with the Tiny Tapeout ASIC demo board.
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Owen Brake
Owen Brake@OwenBrakes·
NoLoRa: Team from Edinburgh demonstrated LoRa transmission on MCUs with no radio chips, by utilizing the 27th harmonic of the SPI peripheral
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BreakingTaps
BreakingTaps@BreakingTaps·
@r0b0t_sp1der Yep GF180! I used all open source tools, they provide a LibreLane/OpenRoad project template (github.com/wafer-space/gf…) that configures the build flow. Just drop in your RTL I went from newbie to taped out in ~2 months. Steep learning curve but mostly the RTL side!
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BreakingTaps
BreakingTaps@BreakingTaps·
Stoked to get the packaged chips and see if they actually work! What a fun project, huge thanks to wafer.space for making this possible!
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BreakingTaps
BreakingTaps@BreakingTaps·
Super zoomed in views are tough since the upper routing and dummy fill-metal obscure a lot of the neat details. Going to try and delayer these with some manual lapping. We'll see how that goes, but since there are only 5 metal layers I'm hopeful we can get something usable 🤞
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BreakingTaps
BreakingTaps@BreakingTaps·
Corner art came out great! 😍
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logic destroyer
logic destroyer@splinedrive·
StealthV
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psychogenic
psychogenic@PsychogenicTech·
Amazing @hackaday europe, in Lecco. @tinytapeout team meet (nothing like inperson), time with @mithro, old friends and new, even met some really cool guy with a swiss accent. Thanks to all who came for making it so awesome!
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tomorrow56
tomorrow56@tomorrow56·
「JLC2KiCad Web UI」を公開しました！ JLCPCB(EasyEDA)のPart Numberを指定するとKiCadの部品ライブラリ形式に変換する"JLC2KiCad"のWebUI版です。 ぜひ使ってみてください tsukutta.app/apps/e79709da-… #Tsukutta #個人開発
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Tim 'mithro' Ansell
Tim 'mithro' Ansell@mithro·
You can make your own silicon with wafer.space too! Our second shuttle run is open at buy.wafer.space with a new $4 USD per die option!
logic destroyer@splinedrive

First silicon just arrived. These dies are from the first wafer of my GF180MCU based Linux SoC KianV, built with a fully open source ASIC flow. This chip was part of the wafer.space GF180MCU run and hardware validation comes next. Big thanks to Leo Moser for help with the ASIC flow and to @mithro and @evezor for their guidance along the way. The picture shows the first dies. More bring up updates soon.

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Marcelo Samsoniuk
Marcelo Samsoniuk@samsoniuk·
@splinedrive @mithro or a more aggressive 4:1 mux for ADDR/DATA into 16-bit and use 4-2-2-2 cycles for 4x32-bit burst, which may be in sync with an external SDRAM in case of cache miss...
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Marcelo Samsoniuk
Marcelo Samsoniuk@samsoniuk·
@splinedrive @mithro well, I am waiting no less than a 3-4 chipset solution for an Amiga500-like machine, modernized with RISCV, SDRAM and VGA frame buffer! 🤣
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logic destroyer
logic destroyer@splinedrive·
@mithro next KianV Stealth performance SoC 👆 wafer.space gf180mcu style
Marcelo Samsoniuk@samsoniuk

@splinedrive @mithro the mux bus concept can be used across multiple chips to handle the MMU/L2/SDRAM (aka north bridge) and another smaller with UART, TIMER and SPI (aka south bridge)... to save pins, the SDRAM 16-bit data bus can be attached directly...

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Tim 'mithro' Ansell
Tim 'mithro' Ansell@mithro·
@Elon_Orbit @splinedrive I'm still trying to make it possible for people to get these dies all wire bonded together with COTS SPI flash and SRAM. That would solve the major issue being the limited amount of SRAM/flash you can fit on the 180nm process technologies.
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Elon Orbit
Elon Orbit@Elon_Orbit·
@splinedrive @mithro 4:1 mux is aggressive but elegant for SDRAM sync. Brings back iAPX trauma - trace latency killed performance. At $4/die, I'm in. Multi-chip finally makes sense.
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Keşfet

@Terasic_FPGA @AlteraFPGA_ @enjoy_digital @mesnavi @MouserElec @crowd_supply @tinytapeout @always_ff_rohan