engineers@work

Test program, to the Z80 the board is real. ;-------------------------------------------------------------------------------------------------------- ;- Celestite LAN Board — Network Stress Test ;- All output on MZ-1500 screen (VRAM D000-D3FF). Loops continuously. ;- Also mirrors summary to debug port (50h). ;-------------------------------------------------------------------------------------------------------- PORT_DBG EQU 050h PORT_MR EQU 060h PORT_AR0 EQU 061h PORT_AR1 EQU 062h PORT_DR EQU 063h PORT_PING EQU 067h CMD_OPEN EQU 001h CMD_CLOSE EQU 010h ST_ESTAB EQU 017h ST_CLOSED EQU 000h TPSTART EQU 010F0h MEMSTART EQU 01200h VRAM EQU 0D000h VL EQU 40 ORG TPSTART ATRB: DB 001h NAME: DB "CELESTITE STRESS", 0Dh SIZE: DW MEND - MEMSTART DTADR: DW MEMSTART EXADR: DW MEMSTART COMNT: DS 104 ORG MEMSTART START: LD SP, 01180h ;- Init W5100. LD A, 080h OUT (PORT_MR), A LD A, 003h OUT (PORT_MR), A ;- Write gateway IP to GAR. XOR A OUT (PORT_AR0), A LD A, 001h OUT (PORT_AR1), A LD A, 192 OUT (PORT_DR), A LD A, 168 OUT (PORT_DR), A LD A, 1 OUT (PORT_DR), A LD A, 1 OUT (PORT_DR), A LD HL, 0 LD (LOOPCNT), HL ;- ============================================================ MAINLP: ;- Clear text VRAM only (D000-D3E7, 1000 bytes). LD HL, VRAM LD BC, 1000 CLR: LD (HL), 000h INC HL DEC BC LD A, B OR C JR NZ, CLR LD HL, (LOOPCNT) INC HL LD (LOOPCNT), HL ;- Line 0: Title. LD HL, VRAM LD DE, S_TITLE CALL PVRAM ;- Line 1: Loop count. LD HL, VRAM + VL LD DE, S_LOOP CALL PVRAM LD A, (LOOPCNT+1) CALL PHEXV LD A, (LOOPCNT) CALL PHEXV ;- ---- PING (line 3) ---- LD HL, VRAM + VL*3 LD DE, S_PING CALL PVRAM XOR A OUT (PORT_PING), A LD B, 250 PNGW: PUSH BC IN A, (PORT_PING) POP BC CP 0FFh JR NZ, PNGGOT LD DE, 12000 PNGD: DEC DE LD A, D OR E JR NZ, PNGD DJNZ PNGW LD HL, VRAM + VL*3 + 28 LD DE, S_TOUT CALL PVRAM JR PNGDN PNGGOT: LD HL, VRAM + VL*3 + 28 CALL PDECV LD DE, S_MS CALL PVRAM PNGDN: ;- ---- TCP CONNECT (line 4) ---- LD HL, VRAM + VL*4 LD DE, S_TCP CALL PVRAM ;- Close. LD A, 004h OUT (PORT_AR0), A LD A, 001h OUT (PORT_AR1), A LD A, CMD_CLOSE OUT (PORT_DR), A ;- Mode = TCP. LD A, 004h OUT (PORT_AR0), A XOR A OUT (PORT_AR1), A LD A, 001h OUT (PORT_DR), A ;- Dest IP. LD A, 004h OUT (PORT_AR0), A LD A, 00Ch OUT (PORT_AR1), A LD A, 192 OUT (PORT_DR), A LD A, 168 OUT (PORT_DR), A LD A, 1 OUT (PORT_DR), A LD A, 1 OUT (PORT_DR), A ;- Port 80. LD A, 004h OUT (PORT_AR0), A LD A, 010h OUT (PORT_AR1), A XOR A OUT (PORT_DR), A LD A, 80 OUT (PORT_DR), A ;- OPEN + CONNECT. LD A, 004h OUT (PORT_AR0), A LD A, 001h OUT (PORT_AR1), A LD A, CMD_OPEN OUT (PORT_DR), A LD A, 004h OUT (PORT_AR0), A LD A, 001h OUT (PORT_AR1), A LD A, 004h OUT (PORT_DR), A ;- Wait. LD B, 250 TCPW: PUSH BC LD A, 004h OUT (PORT_AR0), A LD A, 003h OUT (PORT_AR1), A IN A, (PORT_DR) POP BC CP ST_ESTAB JR Z, TCPOK CP ST_CLOSED JP Z, TCPFL LD DE, 20000 TCPD: DEC DE LD A, D OR E JR NZ, TCPD DJNZ TCPW TCPFL: LD HL, VRAM + VL*4 + 28 LD DE, S_FAIL CALL PVRAM JP HTTPDN TCPOK: LD HL, VRAM + VL*4 + 28 LD DE, S_PASS CALL PVRAM ;- ---- HTTP GET (line 5) ---- LD HL, VRAM + VL*5 LD DE, S_HTTP CALL PVRAM ;- Reset TX pointers (TX_RD=0, TX_WR=0 at 0x0422-0x0425). LD A, 004h OUT (PORT_AR0), A LD A, 022h OUT (PORT_AR1), A XOR A OUT (PORT_DR), A ; TX_RD high = 0. OUT (PORT_DR), A ; TX_RD low = 0. OUT (PORT_DR), A ; TX_WR high = 0. OUT (PORT_DR), A ; TX_WR low = 0. ;- Write request to TX buffer. LD A, 040h OUT (PORT_AR0), A XOR A OUT (PORT_AR1), A LD HL, HTTPREQ HTTPWR: LD A, (HL) OR A JR Z, HTTPWD OUT (PORT_DR), A INC HL JR HTTPWR HTTPWD: LD DE, HTTPREQ OR A SBC HL, DE LD A, 004h OUT (PORT_AR0), A LD A, 024h OUT (PORT_AR1), A LD A, H OUT (PORT_DR), A LD A, L OUT (PORT_DR), A ;- SEND. LD A, 004h OUT (PORT_AR0), A LD A, 001h OUT (PORT_AR1), A LD A, 020h OUT (PORT_DR), A ;- Poll RX_RSR. LD B, 250 HTTPRW: PUSH BC LD A, 004h OUT (PORT_AR0), A LD A, 026h OUT (PORT_AR1), A IN A, (PORT_DR) LD H, A IN A, (PORT_DR) LD L, A POP BC LD A, H OR L JR NZ, HTTPGOT LD DE, 20000 HTTPRD: DEC DE LD A, D OR E JR NZ, HTTPRD DJNZ HTTPRW LD HL, VRAM + VL*5 + 28 LD DE, S_TOUT CALL PVRAM JP HTTPDN HTTPGOT: ;- Show hex count on line 5. PUSH HL LD HL, VRAM + VL*5 + 28 POP DE LD A, D CALL PHEXV LD A, E CALL PHEXV LD DE, S_BYT CALL PVRAM ;- Read HTTP response and display on screen lines 7-24 (18 lines). LD A, 060h OUT (PORT_AR0), A XOR A OUT (PORT_AR1), A LD HL, VRAM + VL*7 LD C, 200 ; Max bytes to display. HTDISP: IN A, (PORT_DR) CP 00Dh JR Z, HTNXT ; Skip CR. CP 00Ah JR Z, HTNL ; LF = new line. ;- Convert and write to VRAM. PUSH HL PUSH DE CALL A2DSP POP DE POP HL LD (HL), A INC HL JR HTCHK HTNL: ;- Advance to next 40-char line. Round HL up to next VL boundary. ;- New HL = ((HL - VRAM + VL) / VL) * VL + VRAM. PUSH DE LD DE, VRAM OR A SBC HL, DE ; HL = offset from VRAM. LD A, L ADD A, VL JR NC, HTNL2 INC H HTNL2: LD L, A ;- Round down to VL boundary: offset = (offset / 40) * 40. ;- Approximate: clear low bits. 40 = 8*5, not power of 2. Use division. ;- Simple: subtract (offset mod 40). Use repeated subtraction. LD A, L LD E, A LD A, H LD D, A HTNL3: LD A, D OR A JR NZ, HTNL4 LD A, E CP VL JR C, HTNL5 HTNL4: LD A, E SUB VL LD E, A JR NC, HTNL3 DEC D JR HTNL3 HTNL5: ;- E = offset mod 40. Subtract from HL. LD A, L SUB E LD L, A JR NC, HTNL6 DEC H HTNL6: LD DE, VRAM ADD HL, DE POP DE JR HTCHK HTNXT: ;- Just consumed CR — skip, don't advance. HTCHK: ;- Bounds check. LD A, H CP 0D4h JR NC, HTEND DEC C JR NZ, HTDISP HTEND: ;- RECV confirm. LD A, 004h OUT (PORT_AR0), A LD A, 001h OUT (PORT_AR1), A LD A, 040h OUT (PORT_DR), A HTTPDN: ;- Close socket. LD A, 004h OUT (PORT_AR0), A LD A, 001h OUT (PORT_AR1), A LD A, CMD_CLOSE OUT (PORT_DR), A ;- Debug port summary. LD HL, DBGLP CALL PSTR LD A, (LOOPCNT+1) CALL PHEX LD A, (LOOPCNT) CALL PHEX LD HL, DBGCR CALL PSTR ;- Delay ~1 second at 3.54MHz (2 × 65535 × 26T ≈ 0.96s). LD B, 2 DLY1: LD DE, 0FFFFh DLY2: DEC DE LD A, D OR E JR NZ, DLY2 DJNZ DLY1 JP MAINLP ;-------------------------------------------------------------------------------------------------------- ;- PVRAM: Write null-terminated ASCII string at DE to VRAM at HL. Returns HL advanced. ;-------------------------------------------------------------------------------------------------------- PVRAM: LD A, (DE) OR A RET Z PUSH HL PUSH DE CALL A2DSP POP DE POP HL LD (HL), A INC HL INC DE JR PVRAM ;-------------------------------------------------------------------------------------------------------- ;- PDECV: Print A as decimal to VRAM at HL. Advances HL. ;-------------------------------------------------------------------------------------------------------- PDECV: PUSH BC LD B, 0 PVD100: CP 100 JR C, PVD10 SUB 100 INC B JR PVD100 PVD10: PUSH AF LD A, B OR A JR Z, PVD10N ADD A, 020h LD (HL), A INC HL PVD10N: POP AF LD B, 0 PVD10L: CP 10 JR C, PVD1 SUB 10 INC B JR PVD10L PVD1: PUSH AF LD A, B OR A JR Z, PVD1N ADD A, 020h LD (HL), A INC HL PVD1N: POP AF ADD A, 020h LD (HL), A INC HL POP BC RET ;-------------------------------------------------------------------------------------------------------- ;- PHEXV: Print A as 2-digit hex to VRAM at HL. ;-------------------------------------------------------------------------------------------------------- PHEXV: PUSH AF RRCA RRCA RRCA RRCA AND 00Fh CALL PHXN POP AF AND 00Fh PHXN: CP 00Ah JR C, PHXN1 ADD A, 001h - 00Ah LD (HL), A INC HL RET PHXN1: ADD A, 020h LD (HL), A INC HL RET ;-------------------------------------------------------------------------------------------------------- ;- A2DSP: Convert ASCII in A to MZ display code via table. ;-------------------------------------------------------------------------------------------------------- A2DSP: PUSH HL AND 07Fh LD L, A LD H, 0 LD DE, ATBL ADD HL, DE LD A, (HL) POP HL RET ;-------------------------------------------------------------------------------------------------------- ;- Debug port helpers. ;-------------------------------------------------------------------------------------------------------- PSTR: LD A, (HL) OR A RET Z OUT (PORT_DBG), A INC HL JR PSTR PHEX: PUSH AF RRCA RRCA RRCA RRCA AND 00Fh ADD A, 030h CP 03Ah JR C, PH1 ADD A, 007h PH1: OUT (PORT_DBG), A POP AF AND 00Fh ADD A, 030h CP 03Ah JR C, PH2 ADD A, 007h PH2: OUT (PORT_DBG), A RET ;-------------------------------------------------------------------------------------------------------- ;- Strings (ASCII, null-terminated). ;-------------------------------------------------------------------------------------------------------- S_TITLE: DB "CELESTITE NET STRESS TEST", 0 S_LOOP: DB "LOOP ", 0 S_PING: DB "PING 192.168.1.1", 0 S_TCP: DB "TCP CONNECT GATEWAY 80", 0 S_HTTP: DB "HTTP GET GATEWAY", 0 S_PASS: DB "PASS", 0 S_FAIL: DB "FAIL", 0 S_TOUT: DB "TOUT", 0 S_MS: DB "MS", 0 S_BYT: DB "H", 0 HTTPREQ: DB "GET / HTTP/1.0", 0Dh, 0Ah, 0Dh, 0Ah, 00h DBGLP: DB 0Dh, 0Ah, "Loop:", 0 DBGCR: DB 0Dh, 0Ah, 0 LOOPCNT: DW 0 ;- ASCII to MZ display code table (128 bytes). ATBL: DB 0CCh,0E0h,0F2h,0F3h,0CEh,0CFh,0F6h,0F7h DB 0F8h,0F9h,0CDh,0FBh,0FCh,0CDh,0FEh,0FFh DB 0E1h,0C1h,0C2h,0C3h,0C4h,0C5h,0C6h,0E2h DB 0E3h,0E4h,0E5h,0E6h,0EBh,0EEh,0EFh,0F4h DB 000h,061h,062h,063h,064h,065h,066h,067h DB 068h,069h,06Bh,06Ah,02Fh,02Ah,02Eh,02Dh DB 020h,021h,022h,023h,024h,025h,026h,027h DB 028h,029h,04Fh,02Ch,051h,02Bh,057h,049h DB 055h,001h,002h,003h,004h,005h,006h,007h DB 008h,009h,00Ah,00Bh,00Ch,00Dh,00Eh,00Fh DB 010h,011h,012h,013h,014h,015h,016h,017h DB 018h,019h,01Ah,052h,059h,054h,050h,045h DB 000h,001h,002h,003h,004h,005h,006h,007h DB 008h,009h,00Ah,00Bh,00Ch,00Dh,00Eh,00Fh DB 010h,011h,012h,013h,014h,015h,016h,017h DB 018h,019h,01Ah,053h,000h,058h,000h,000h MEND:

MZ-700/MZ-1500 Networking Virtualised Mr Ishi's Celestite LAN board on the picoZ80 - uses WiFi or NCM (network over USB). cwaweb.bai.ne.jp/~ohishi/zakki/… Just need to find software now otherwise I will have to write a driver for BASIC MZ-5Z008 that I disassembled and add a read/write NFS driver or similar.

picoZ80 v2.5a first test in an MZ-1500. Persona created, will look to add virtual MZ-1R23 Kanji board, PIO-3034 320K EMM board, MZ-1R37 640K EMM board and even the Celistite LAN Board (via Wifi/NCM).

Git repo updated with latest code, schematics and pcb files. Release 2.472 files available with many improvements.

Latest update, pico in Black. Minor update but routing redone to limit RF interference (to help pass FCC/RED tests if required). Latest firmware updates utilise the ESP32 OTG USB network so you can run the web interface without WiFi being present.

MZ-700, MZ-80A and now MZ-2000 Persona's added to the picoZ80. Major changes made, now full ICE debug shell added with improved Z80 physical timing, performance and USB network (web interface). Video: MZ-2000 running in physical mode with virtual floppy drive. See documentation @ eaw.app/picoz80/.

picoZ80 - first try in an MZ-80A, vanilla mode. Hostile environment with high voltage just above the picoZ80 board (CRT), no issues. Boots floppy disk drive, boots tape. Next step, write some persona drivers for virtual floppy, virtual UROM, RFS etc.

picoZ80 repo now on git (git.eaw.app/eaw/pico), along with the User Manual (eaw.app/picoz80-userma…), Technical Guide (eaw.app/picoz80-techni…) and Developers Guide (eaw.app/picoz80-develo…). Basic and MZ700 Personalities exist, additional persona under development.

This it the twenty-dollar question! My aim is to place the designs/software onto git and it will be open source and people can build as they like. If some Chinese manufacturer got involved they would be very cheap as they are common parts but for 5 off assembled it was costing me ~50GBP each. PCB+parts from Mouser to self-build work out around GBP20, but this is paying top dollar for <10 parts.

@engineerswork1 Awesome, now where can we buy them?

@r0b0t_sp1der Yep, just busy putting all into git (minus the plethora of temp files)! Probably this w/e or Easter and will be up on git.

@engineerswork1 Oh - are you going to put the Kicad files up online?

I've done both and if I could have got an FPGA small enough with enough BRAM and ALM's, I wouldnt have thought about using the RP2350, glad I didnt as it is a nice device. I would imagine you could keep redcodes Z80 emulator for an 8080, Z80 is a superset, just need to rewire the PCB for the pin differences and change the PIO's, 2 PIO's sampling the clocks and setting IRQ's which other PIO's pickup to activate the bus cycles. On my website are past FPGA replacements for the Z80 which work well but they are well oversized and more tailored for the Sharp machines! My last board, eaw.app/tranzputer-fus… is still waiting completion, just need to get a fab to make me one as my own reflow build had many bad bga joints and trying to use a hot air station to fix just compounds the issues.

@engineerswork1 Awesome, thanks dude. I'm torn. I'd probably learn _more_ doing it this "emulation" route than just with an FPGA. But it should just be a pin scramble and some code ...

Yes, I've published the schematics and documentation at eaw.app/picoz80/ and will soon put the whole software/hardware repo up on git. An 8080 would probably be a bit of work, the pins are in different locations and the clocks/multi-voltage may be tricky, a bit like the pico6502 Im also working on for clock phasing and the multi-voltage shouldnt be an issue as reading the specs, the outputs are >=0v. 8088 should be very possible too, as would the muxed 8086.

@engineerswork1 Astonishing work. I was noodling around with something like this, but for 8080 and TMS9900. Maybe via FPGA. But when you have 200Mhz and the PIO, pretty much don't need it. Are you going to release the designs? It _probably_ would work as a pico8080 or pico8086 already ...

The logic thresholds for TTL is 0.8v or below = 0 and >2.0V = 1 - thus driving at 3.3V, so long as the motherboard of the host doesnt have very long PCB lands or many attached devices, you could drop to 2.3V and still see logic 1. Input side is the same, the RP2350 will see 5V as logic 1 which is > 2.0V so fine and < 0.8V as logic 0. This article gives you a good insight: hackaday.com/2016/12/05/tak…

@engineerswork1 How 40yo devices handle 3v3 signalling without level shifters? I know Pico is at least partially 5v tolerant, but can't emit that.

Documentation on my projects updated at eaw.app - now includes a Japanese version, translated courtesy of Claude. Working with Grok for over a year, now switching to Claude due to primary work requirements, I must say Claude is very good. Grok is excellent but not being able to view your code repo or update it is a major limiting factor that I hope xAI address. Claude has its issues, you need to be topic and programming aware to correct oversights and mistakes, but I hope to use AI more in the future to enhance and further my projects.

It is certainly possible to add ICE functionality, just time! I think the best method would be over a web browser, CLI would be easier to implement as it would operate directly within the RP2350 and finer control but Web based would be more user friendly. Will give it some thoughts.

@engineerswork1 Wow, I had a very similar idea in my head for quite some time (but not enough spare time to actually execute it). My main motivation was what @gojimmypi asked about, though - in-circuit emulation / debugging.

New version of picoZ80, v2.5 - adds a USB hub to enable direct connection with the RP2350B and ESP32. Documentation now at eaw.app/picoz80 - MZ700 persona all but complete, tidying up code base before moving onto the MZ-80A persona.

Thanks. I’m not familiar with the ZX ULA but you could virtualise it as a driver in the codebase. Passing through to physical for core ram and the extended request intercepted within the RP2350 and routed to/from internal PSRAM, the physical wouldnt see a bus cycle (except a Refresh cycle if needed). You would create a 1:1 map of the ULA state and registers internally via write through and then decide in the code wether to access physical hardware ram based on this known state. On a 1K ZX-81 it would be easy by just adding the ram via json config, but once you start using custom banking then it needs to be done via a driver which is host aware, hence the concept of persona’s such as the one I wrote for the MZ-700 as it too has internal ram banking.

@engineerswork1 Cool project. Is it feasible to "port" this project for ZX Spectrum, including mem/io emulation? It could serve e.g. as upgrade from 48k to 128k as well. I see some specific issues: ULA accessing (possibly emulated) RAM and partial I/O ports decoding in ZX (for emulated I/Os).

Refactor in this case as Ive built the project from blocks of my other tranzputer designs and need to make it uniform. The RP2350 code was originally C++ with C hooks but after some heavy debug sessions and need for speed, converted it all to C. The ESP32 is in C++. I also used Grok for some of the PIO work to ease the learning curve and my experience with Grok has been 2 steps forward (wow, look what its done), 1 step back and a lot of hard debugging! Currently working with Claude, will see how it helps and how many bugs it introduces in code factoring!!!

@engineerswork1 @psxdev Every time I hear the word "refactor", I envision this loosely knitted sweater... with just one thread dangling... that gets pulled a little. And then a cartoon disaster. Lol. I'm super happy that Visual Studio and other editors have such robust rename and refactor features!

I currently use gdb connected to the SWD port of the RP2350, core 1 runs the Z80 so it is possible to place break/watchpoints and see the Z80 state/memory. It would be possible to add some kind of interpreter running on core 0 connect via the USB to issue commands/set break points but this would need development. Also possible to develop a web based interface via the ESP32 to set/debug the Z80 on the RP2350. Will keep it in mind, at the moment just concentrating on getting this project to an initial completion state where I can publish on github and others can adopt/enhance as needed.

@engineerswork1 Any chance to have a single step debug, breakpoint, JTAG like debugger? Perhaps the RPi debugger would work for this? But to get it to recognize Z80 instructions... Hm

@Denysko_Bublyk The picoZ80 was initially developed in the RC2014 Mini at 7.37MHz. It runs at 8MHz fine, I dont have any test machines which exceed this speed (yet!). QFP though, not sure all the parts would fit without going oversize!

@engineerswork1 Next step is qfp version and up to 20 MHz support