ST010-14
13.3K posts

ST010-14
@st01014
Code synthesizing Carbon-Silicon based lifeform 🖥️🧬 #Coding #Math #Physics #HPC & #AI #RetroTech #Aerospace #AESTHETICS Random #Nerdiness & #Shitposting

I have been very impressed by @SemiAnalysis_ . I think of myself as a wide ranging systems engineer, looking for value at every level from the chip specs to the user interface, but SA exposes me to additional levels of "the system", both above (datacenters) and below (semiconductor fabrication). It probably puts me in "just knows enough to be dangerous" territory. Neat things I learned today: Some of the 800VDC datacenter design choices leverage parts commoditized by electric vehicles. There is now a SiC MOSFET that can operate on 10kV electricity, opening up the possibility of working directly with medium (ha!) voltage AC power transmission lines without stepping down.


every time i'm in the CPU mines. i'm reminded that assembly is a really high level language


if there was an award for coolest looking CPU ever i think the PowerPC G4 chips would win


void xorSwap (int* x, int* y) { if (x != y) { *x ^= *y; *y ^= *x; *x ^= *y; } } One of the most clever and the worst performing methods of swapping 2 numbers. Came across this gem as I attempted to learn prog from scratch, and got some good flashbacks to my second year when I found this trick, worked out a couple examples, and was adamant on using this everywhere I could!




coolest looking and coolest....you know...👀



继续思考, 华为在挑战里面没有谈散热,这是我比较诧异的。 目前两层堆叠,我觉得还有些散热的解法,但如果到三层Active Logic Stack或者更多之后,散热会从工程问题变成架构主问题。。。 目前流行的双层堆叠的技术AMD V-Cache,Intel Foveros和TSMC SoIC,还属于用冷cache叠热logic,因为SRAM功耗较低,热密度低,可用做Top Die,所以散热还能接受。 结构如下所示: SRAM |||| CPU 但华为的论文里是Logic-on-Logic。 即: Active Logic |||| Active Logic |||| Active Logic 这就完全不同了,这种多层Active Logic,热无法横向扩散,所以中间的Logic Die直接变成了烤箱,传统散热是完全扛不住的。 三层或者三层Active Logic堆叠之后,必须进入主动式散热时代!冷却液必须进入封装内部。 变成, Active Logic + Microfluidic Channel |||| Active Logic + Microfluidic Channel |||| Active Logic + Microfluidic Channel 液冷液冷液冷是关键!关键得说三次。。。 以后芯片设计里面需要Thermal Topology Architect,因为:热路径本身会决定Layout。 对的,本人的判断是:华为将来3层和3层以上的LogicFolding路径里面,Thermal将是最大的未解难题,甚至比EDA还难!


















