bastian, bl0x

#openFPGALoader v1.1.0 is out! 🎇 Highlights in this release: - BPI (parallel) Flash support - SPI flash access for @latticesemi ECP3 - Improved CertusNXPro support - Build time enable/disable for cables & vendor drivers - dirtyJtag improvements - Full IDCODE support for @AMDembedded Spartan, 7-Series & Ultrascale+ - Documentation updates Thanks to all contributors/users 🍻 Full release note here: github.com/trabucayre/ope…

Teaching FPGAs and Microcontrollers to Share FPGAs and microcontrollers can be used alternatively in some applications, but they can also be used cooperatively. FPGAs provide ultimate flexibility, but microcontrollers often include peripherals like USB or wireless interfaces that may be more convenient for communications and updates. Both devices require supporting circuitry like power, reference clocks and storage. Fortunately, these can often be shared when using FPGAs and microcontrollers together. My CycloMod board is an example of an FPGA and microcontroller working cooperatively. The board combines a Raspberry Pi RP2350 MCU with a Cyclone 10LP FPGA in the SparkFun MicroMod form factor. In this board I connected the FPGA to the majority of the I/O and use the RP2350 to provide a flexible USB interface. I leverage the bootrom in the RP2350 for firmware and FPGA image updates. The MicroMod form factor is quite compact, which necessitates sharing as there is not much room for multiple oscillators or flash devices. The 12 MHz crystal oscillator in the RP2350 is easily shared by routing it to one of the GPIO clock outputs. Both the Cyclone 10LP and RP2350 rely on external storage, but this can also be shared. On this board the flash is connected to the RP2350 to take advantage of the UF2 loading provided in the bootrom, and the RP2350 loads the Cyclone FPGA. The Cyclone 10LP supports active configuration with an external SPI flash device, but it can also be configured passively through JTAG. Most microcontrollers lack native JTAG host ports, but it is rather straightforward to bit-bang on GPIO and there are a variety of resources available. SVF is one format for scripting the JTAG instructions required to load a device, but the files can get quite large. JEDEC JESD71 Standard Test And Programming Language (STAPL) is another format that includes more advanced elements like loops for reduced file size and it also includes a byte code option for further efficiency. The STAPL byte code format is compact enough to be used with microcontrollers like the RP2350. Altera, who created the STAPL format that they also refer to as JAM, provides source code for implementing the “players” to process these files in embedded systems. This has always been intended for customers to re-use in embedded systems, but they recently applied the MIT-0 open-source license for better clarity. They offer players for the ASCII (JAM) and byte-code (JBC) versions of the files. Altera’s Quartus tools provide the option to generate JAM and JBC files. Since STAPL is a JEDEC standard, other FPGA vendors also support generating these files. Using the open-source code provided by Altera, the RP2350 is able to read a JBC file from flash and load the Cyclone 10LP FPGA through the JTAG interface without a second flash device. I created a python script to convert the JBC files to the UF2 format the RP2350 uses for drag-n-drop programming. The script also adds a header with the file length and other details. Thanks to the ingenuity of the UF2 format created by Microsoft, this enables cross platform field updates with zero software to install. Porting Altera’s JBC player to the RP2350 allowed me to save a flash device and enable user-friendly drag-n-drop FPGA updates.

@Andercot We've ditched all of labview in our experiment facility and replaced with EPICS control system.

LabView is the most insultingly dog shit software on the planet and sits behind 95% of all scientific discoveries in physics and chemistry.

get into FPGAs. they’re not as hyped as AI or robotics, but they’re the hidden backbone of both. you want speed? determinism? ultra-low latency? hardware-level parallelism? that’s FPGA territory. every serious system; autonomous vehicles, defense tech, high-frequency trading, industrial control; runs faster because some engineer somewhere mastered reconfigurable logic. software gives you flexibility. hardware gives you performance. FPGAs give you both. learn VHDL or Verilog. build a simple CPU. implement a PID controller. accelerate an ML inference. you’ll suddenly see how computing really works; not just in code, but in electrons. FPGAs are the bridge between hardware and software thinking. and if you can master that bridge, you become dangerous.

I had to combine the PA and AFE in the Framework laptop SDR. The split approach took too much space away from the filter banks. Although less modular, the new implementation allows for 4x RX and 4x TX, and is a much cleaner mechanical integration. I also switched to skived heatsink which is much more affordable in low volumes than the zipper fin heatsinks

Two decades ago, Arduino put a microcontroller in every student’s hand, revolutionizing grassroots education. Today, as Arduino begins a new chapter in another domain, we’re opening the next chapter in education: putting FPGAs into every student’s hand. We’re delighted to introduce Shrike-Lite, the world’s most affordable FPGA development board, priced at just ₹349 / $4. Shrike-Lite combines an MCU (RP2040) with an FPGA (ForgeFPGA – 1K LUT) on a single board, unlocking hands-on learning for thousands of students and makers. Even with a 1K LUT FPGA, you can build: – Custom UART / SPI / I²C cores – LED and PWM drivers – Simple robotics controllers – Tiny accelerators and logic blocks – Many more digital-logic projects Since Shrike-Lite is a pet project at Vicharak, we’re keeping everything open-source, hardware, software, and toolchains, with complete software support from our team. We’re opening pre-orders for the first 1,000 units in India, starting now. Which will be delivered by 15th Nov, 2025.

Icepi Zero @latticesemi ECP5 FPGA board follows the Raspberry Pi Zero form factor. cnx-software.com/2025/08/21/ice… The open-source hardware board is equipped with a microSD card slot, three USB-C ports, a GPDI mini connector for video output, and a 40-pin GPIO header. The Lattice ECP5 FPGA (24K LUTs) board can emulate many systems, from the Apple I and the Oberon to the Commodore 64, and can also be used for FPGA gateware experimentation using open-source tools such as Icestudio.

Generative AI meets RF circuit design = game changer • Passive networks tailored by diffusion models. • Specify stop-band/pass-band; AI does the rest. • Pixel patterns are not intuitive to electrical response. Designs getting more abstract. Prepare for a cognitive shift.

Aquarian Ford Taurus A strike on the box Ooh, Ford Focus Roberta Flack, Donny Hathaway Frank Sinatra #1612 #vulf

Great work, Michael! A Constant-Fraction Discriminator For Sub-Nanosecond Timing Quelle: Hackaday search.app/9HVFy

Want to play with the Zynq hard processor system with a full open source toolchain? You can! Many thanks @regymm0 for implementing Zynq HPS support for the openXC7 open source FPGA toolchain, and for providing this demo: github.com/openXC7/demo-p…

Leonardo Romor wrote a C implementation of the python fasm (FPGA assembler), which he says is up to 10x faster than the python implementation. This will be an exciting addition to the openXC7 open source FPGA toolchain! github.com/lromor/fpga-as…

I heard the sounds of a thousand DIY chip fab projects dying. Super sad Hey @efabless a month ago all was well and now this? efabless.com/news/a-year-of…

KiCad Version 9.0.0 Release The KiCad project is proud to announce the latest major version stable release. See the blog post on the KiCad website for more information about this release. kicad.org/blog/2025/02/V…

So, now that v9 is out, you're going to want to learn how to use all the awesome new features, right? Have we got a place for you! kicon.kicad.org KiCon Returns to North America, May 28-30th, San Diego, CA. Pre-sale discount tickets are available now!

Genius, sad to hear he's gone.

I spent years making Functional Programming more accessible. I thought the tech is great but it just lacks educational resources. So I legit spent 6 years writing articles and mentoring people on OSS projects. Forget that. Turns out, most devs don't even know trivial things like binary trees. If the following code isn't immediately obvious to you, ngmi. My New Year resolution for 2025 is to focus on more impactful ways to promote OCaml, Functional Programming and Category Theory ideas.

#1612 #vulf

Follow the white rabbit...