VirginCMOS

@zipcpu The Scottish vs English slang issue. In reality, big-endian vs little-endian is a much bigger ,almost like two different languages. But I just wanted to mention a simple Scottish vs English analogy.

Here's a bug from this weekend: In this case, two bugs canceled each other out, leaving me believing the design worked in a configuration that I'd never hardware tested it in. Also, a good question, how good should a "self-checking" test bench be? You can read more about this bug here: github.com/ZipCPU/sdspi/i…

@furan My bad. What I meant is that I’ve never tried boundary scan. I’ve done normal UART debugging, but I have no idea how one would discover components on a board through JTAG debugging. N.B: LLM can guide. Just trying to find what people used before LLM to learn that.

@VirginCMOS how are you doing anything with FPGAs without JTAG?

probe_passive now supports pinfiles for grabbing the current state of named pins over JTAG.

more of the 3D pipeline online

At this point New Zealand should be given to Indians. They will live there. I don't claim they make it prosperous or good. But it will be inhabitated.

@always_ff_rohan In an indirect way I meant the same. Instead of dieshot i thought to write stolen dieshot. Actually intellectual properties are not private any more. Steal/develop the IPs, no one care if your country has nukes and not afraid of the US. The actual blocker is lithographic tech.

@VirginCMOS I'm asking - Can I produce a equivalent chip design at volume without triggering legal retaliation from the player who owns the original design?

These are bare dies of the Kintex-7 XC7K325T and its pin-compatible Chinese clone, the JFM7K325T from Fudan Micro. Only difference is that GTX transceivers of JFM7K325T behave differently, so the xilinx pcie core wouldn't work by default. The real question is that where do you draw the line on democratizing silicon?

I think the $4 Shirke-lite (RP2040+ForgeFPGA) dev board could become a surprisingly capable FOSS JTAG endpoint for OpenOCD, OpenFPGALoader, and maybe even vendor tools.

@FPGA_Zealot Seeing JTAG on this stuff for the first time. Anychance to post a short video?

@ATaylorFPGA Why choose RPI over STM32 controllers? The ethernet PMOD uses an SPI interface?

Fridays are for demos! What demos I am hoping to be able create with the newly arrived updated S7 Development board. This one has the S7-50 device and the RPI Pico. I also received new Pmods for testing Ethernet and HMDI Tx and Rx.

Looks like the HDMI Rx and Tx Pmods are working

@furan Group created? Pls add me too

200 or so responses to the FPGA group chat, I guess I should have expected that. I'll create it tomorrow.

Feel free to join the discussion of what makes an ideal memory controller on Reddit. reddit.com/r/ZipCPU/comme…

@ATaylorFPGA Thanks for the blog, Adam! I haven’t had a chance to check the full implementation yet, but is there any chance you could share the Python code used here?

This week, I created a fun RTL project which reads data from accelerometer, gyroscope, temperature and pressure sensors. All the RTL is provided if you want to work with these sensors in other projects. adiuvoengineering.com/post/microzed-…

Well, let's think about that. What would constitute a "truly ideal memory controller IP"? Here are my thoughts. Let me know if I missed anything.

Between planning and building: 1. Plans become promises, goals, and even contracts 2. They can also be used to solicit investment Most of my planning is now done. Let's see how much we can get done on a "day off" / holiday.