Guy Eschemann

1.4K posts

Guy Eschemann banner
Guy Eschemann

Guy Eschemann

@geschema

FPGA wizard at @PLC2GmbH, software developer, dad and guitar rookie. Natural health enthusiast. Creator of https://t.co/T4N9bTQl4S. Opinions are my own.

Marckolsheim, France เข้าร่วม Aralık 2008
76 กำลังติดตาม965 ผู้ติดตาม
Guy Eschemann รีทวีตแล้ว
Dr Sarah Myhill
Dr Sarah Myhill@MyhillNews·
Please donate to my GMC Judicial Review Fighting Fund. See dailymail.co.uk/news/article-1… Please donate to Sarah Myhill Limited Sort code 20 61 08 Account number: 50760242 Many thanks, Sarah
Dr Sarah Myhill tweet mediaDr Sarah Myhill tweet mediaDr Sarah Myhill tweet mediaDr Sarah Myhill tweet media
English
1
6
15
1.4K
Tess Falor, Ph.D. | Renegade Research
1) PEM - pacing & started cutting back/staying within my energy envelope 2) MCAS - Cromolyn sodium, antihistamines, baby aspirin 3) Dysautonomia - compression garments, salt 4) Craniocervical instability - physical therapy, biophysical chiropractor 5) Jugular Eagle syndrome - Plavix, then styoidectomy surgery 6) Cerebrospinal fluid leak - healed itself after I lowered intracranial pressure 7) Muscle pain/restless legs/cognitive dysfunction - Low Dose Abilify 8) Migraine w/brainstem aura - Nurtec
English
2
12
51
10.6K
Guy Eschemann รีทวีตแล้ว
Whitney Dafoe
Whitney Dafoe@DafoeWhitney·
I want to have gone into my doctor’s office at my college 19 years ago, when I felt like I had a fever.. See a specialist, get diagnosed with some condition and have them give me a bunch of those marvelous shiny color brochures… New post on my blog: whitneydafoe.com/mecfs/?post=th…
English
9
56
220
12K
Guy Eschemann
Guy Eschemann@geschema·
The latest version of @Sigasi Studio can warn you about forgotten reset values in clocked VHDL processes. Such a useful feature! #incomplete-reset-branch" target="_blank" rel="nofollow noopener">insights.sigasi.com/releasenotes/s…
English
0
0
3
256
Adam Taylor
Adam Taylor@ATaylorFPGA·
A few Avnet ZU1 boards arrived for some training we are going to be doing.
Adam Taylor tweet media
English
6
2
59
3.4K
Guy Eschemann
Guy Eschemann@geschema·
Xilinx recommends to keep the number of unique control sets below 7.5 % of total slices to avoid impacting timing and placement. In Vivado, you can query the number unique control sets in your design using the "report_control_sets -verbose" command.
English
2
0
6
266
Guy Eschemann
Guy Eschemann@geschema·
A sometimes overlooked metric in Xilinx #FPGA designs is the number of unique control sets—a control set being defined as the combination of a clock, a clock-enable and a reset signal. Too many control sets prevent the efficient packing of logic into slices.
English
1
2
10
1.1K
Sigasi
Sigasi@Sigasi·
Happy Friday! The Sigasi offices are places of intense productivity - and that requires fuel. We recently updated our fruit & dried nuts station, through much hard work by our engineer Michiel 🤗 🌰🥜🍏🍐 What do you and your colleagues snack on?
Sigasi tweet media
English
1
1
4
224
Guy Eschemann
Guy Eschemann@geschema·
As a last resort, use out-of-context synthesis to compile the troublemakers with special options. (4/4)
English
1
0
0
112
Guy Eschemann
Guy Eschemann@geschema·
Optimize your RTL code down to an acceptable number of logic levels, based on the rule of the thumb above. (3/4)
English
1
0
0
129
Guy Eschemann
Guy Eschemann@geschema·
Use rules of the thumb, such as 500 ps per logic level, to estimate whether your design has a chance to work at the target clock frequency. (2/4)
English
1
0
0
120
Guy Eschemann
Guy Eschemann@geschema·
When it comes to #FPGA timing closure, it's a good idea to keep an eye on the number of logic levels in your design. In Xilinx (oops, AMD) Vivado you can do this using: report_design_analysis -logic_level_distribution -extend Do it post synthesis to save time! (1/4)
English
1
3
4
335
Guy Eschemann
Guy Eschemann@geschema·
A public service reminder to always keep your #FPGA logic under reset while its clock-generating circuit (PLL or MMCM) is not locked. This is especially important for stateful logic like FSMs.
English
1
3
20
1.5K
Zip CPU
Zip CPU@zipcpu·
Does any one have a good example of "shuffling logic from one clock to another" in order to meet timing? I have a student asking who is asking for examples ...
English
5
2
4
1.8K
Guy Eschemann
Guy Eschemann@geschema·
A good teacher makes me feel like I can fly; a bad teacher gives me the feeling that I'm not smart enough.
English
0
0
2
208
Guy Eschemann
Guy Eschemann@geschema·
@zipcpu And so does quality. When a client comes up with a made up number like that, I ask if he would accept the roof on his house to be only 95% waterproof ;-)
English
1
0
2
97
Zip CPU
Zip CPU@zipcpu·
@geschema Why not 100%? Because cost goes up the higher you go.
English
1
0
2
140
Zip CPU
Zip CPU@zipcpu·
Customer asks for 95% test coverage. As it turns out, 95% test coverage takes a lot of work.
Zip CPU tweet media
English
3
0
8
2.8K