Steven Armour

Rectangular EM TM11 Waveguide (Now in Color) with @SymPy, Xarray, @yt_astro using all @NumFOCUS projects. Showing what @ThePSF can do for scientific Learning/Computing/Visualization github.com/PyLCARS/YT_Bey…

@Aaronia_AG I have had rf devices fail because the rf section was not isolated from the DC bias and the wire bound/dc input impedance parameters had not been studied/constrained. I would love for a load pull/push for dc/broadband via probe to find out the wire bound allowed impedance

@ArmourMSG True.

140GHz Chip Bonding - Pure Magic🦄 #Aaronia #RF #Tech #Microwave #SDR

@TracketPacer I have always seen bit banging as a combo of " poking the bear with a stick"/"fuck around and find out" kludge solution to trying to talk to a device cause we dont know a better way to do it

ok legitimately tho wtf is bit-banging

> be me, Intel > world domination status: achieved > have a license to print money with x86 > life is good > be 2007, some fruit company named Apple shows up > "hey can you make a chip for our new phone?" > my CFO brain activates > look at their offer... pathetic > my margins! my beautiful margins! > "lmao no," I tell them, "get that low volume, low margin peasant shit out of my office" > tell them to go bother some Korean foundry > they call it the "iPhone" > it only sells, like, a bazillion units > oops.mp4 > should have listened to my gut, but my gut was too busy counting shareholder dividends > speaking of shareholders > CEO is now a finance bro > innovation is for nerds, stock buybacks are for chads > spend $36 billion to make line go up > R&D? how about R&Buyback > TSMC and Samsung are building fabs? cute. > we're building value for our shareholders > meanwhile, in the basement... > be AMD, literally on life support > selling their HQ to pay the rent > "hey guys what if we made a good CPU for once?" > entire Intel leadership room dies of laughter > we're still milking 14nm++++ for the fifth year in a row > what are they gonna do, beat us with... checks notes... core count and efficiency? > HQ focused on PPT presentations and buybacks > R&D team: "hey we have this 10nm design but it's kinda... impossible to manufacture?" > me: "JUST MAKE IT WORK, I HAVE A DIVIDEND TO ANNOUNCE" > requirement: quadruple the transistor density, tooling: from the stone age, yield: literally negative > "10nm is fine, everything is fine" for five years > entire company is stuck on 14nm++++++++ > watching AMD just call TSMC and get a shiny new 7nm node like it's nothing > suddenly, AMD's "Zen" thing is actually good > gamers and redditors are calling me a "dead company walking" > my stock is in freefall > panic.jpg > hire back Based Pat Gelsinger to save us > Pat comes in: "what in the goddamn..." > find out we're now outsourcing our own chips to TSMC > mfw we missed mobile, lost the process lead, got rekt by AMD, and our grand plan is to ask the government for money > mfw we're now a fabless fab with an identity crisis > mfw the once-proud "Intel Inside" is now "TSMC Inside" > at least the shareholders had some good quarters > company_cope.jpg

@lauriewired I carry a small role of red electrical tape in all my bags to cover all the blue LEDs at home or when traveling

Why are all electronic indicator lights blue? The Purkinje effect causes human vision to get more sensitive to blue hues at low illumination. Blue Leds give roughly ~20x the luminous intensity of red or green indicators. It's also really, really annoying at night:

@AnthropicAI Love the new model; but can you figure out the Claude website cause your either updates or dynamic scanning is causing the page to drop the prompt I am writing in the chat in the middle of writing it or closing the artifact I have open and it is getting old fast!

Today we're releasing Claude Opus 4.1, an upgrade to Claude Opus 4 on agentic tasks, real-world coding, and reasoning.

@lauriewired At what point do we stop with the ultrabroadband single data channel per physical lane PAM-N SERDES and move to coherent with multiple "narrow band" data channels per physical lane? Where now at 64+ equalizer taps per receiver per lane. SERDES is too SI inefficient to continue

PCI link bus designs are incredibly complex. Standard FR-4 PCB material is basically at its limit. Every year it's harder to keep up with the new standards. At what point do we flip the architecture on its head... GPU as the motherboard, CPU as the peripheral?

@lukeweston @ico_TC @ID_AA_Carmack @abrogationism Would it really be that efficient to continuously run 4" wafers if we had a more continuous process flow than all the pickup and go run around with the current FOUP system? at least above ~50nm tech.

@ico_TC @ID_AA_Carmack @abrogationism 1 micron is pretty easy. You can get to 1 micron with direct-write, maskless optical photolithography (i-line 365nm from Hg lamp.) 4” wafer tooling very common, practically the standard, in university labs, but no “real” fab would use inefficient 4” wafers today- big is better.

A state of the art fab today may be the most complex and sophisticated thing built by humans; you can’t “just go build one” and compete with TSMC given any amount of resources. However, they are general purpose systems with a lot of flexibility. How much simpler could they get if the MVP was a single chip design, and is there low hanging fruit in the design space where you can trade off some level of design performance to usefully simplify the fab? Basically, if Apple or Tesla wanted to start a personal fab, as big tech companies used to do decades ago, how much less impossible would it be versus competing head on for arbitrary designs?

Having to be nurse ratched to a stubborn senior & now diabetic cat is not fun.

@ico_TC 1. thanks this is really cool; 2. OpenVAF is not a TCAD (could be leveraged on top of for compact extraction). The only open-source non just research paper ones I know of are devsim.org/index.html & charon.sandia.gov

@ArmourMSG You might want to look at openvaf.semimod.de

Q: how many folks know what TCAD is, have been absolutely frustrated by the barriers to using/ learning it? If you have crossed that barrier, been utterly frustrated by most TCAD sys antiquatedness, kind of failure to deliver on material science realization to commercial devices?

What if, instead of targeting TikTok, Congress went after companies that sell our data to the higher bidder, or made social media companies disclose their algorithms, or went after Silicon Valley in a meaningful way?

This but I’m sure videos like this are why they want to ban it

Mark Cuban laid into pharmacy benefit managers at the White House today. Three PBMs, middlemen owned by giant healthcare firms like CVS and UnitedHealth, dominate how drugs are priced. And they’re price gouging essential drugs at the expense of patients in need. @mcuban

digital scan control on a JEOL 840 with the OBI (open beam interface). you can build it yourself for ~$600 in parts. old SEMs still get great resolution! you could turn this into an ebeam lithography setup too

Started a blog-like thing on Git Hub. The first post is on a tool to ease content extraction from Jupyter notebooks by scouring cells for `%%writefile`/`#%%writefile.` github.com/GProtoZeroW/UC…

🐍📰 MicroPython: An Intro to Programming Hardware in Python In this tutorial, you'll learn about MicroPython and the world of electronics hardware. You'll set up your board, write your code, and deploy a MicroPython project to your own device. #python realpython.com/micropython/

How do companies ship code to production? The following describes a typical software delivery workflow. Companies have diverse environments using different tools. This is one representative workflow that demonstrates some common practices. Details will differ across organizations. With that context established, the general steps are as follows: Step 1: The product owner creates requirements and stories. Step 2: The development team prioritizes stories and organizes sprints. Step 3: Developers commit code to the version control system. Step 4: An automation server builds the code and runs tests. Code coverage and quality checks are performed. Step 5: If the build succeeds, artifacts are stored in the artifact repository. The build is deployed to the developer environment. Step 6: Features are tested independently in multiple isolated environments. Step 7: The QA team tests the features in QA environments. Various forms of testing are performed. Step 8: Once verified, the build is deployed to a user acceptance testing environment for final validation. Step 9: Release candidates that pass testing can be deployed to production based on the release schedule. Feature flags and incremental rollout techniques manage risk. Step 10: The site reliability team monitors production and reports issues. Teams prioritize and fix issues according to defined policies. How does your organization's software delivery workflow differ from the process outlined here? What tools and techniques have you found most effective? I'm interested to hear about the various approaches across the industry. – Subscribe to our weekly newsletter to get a Free System Design PDF (158 pages): bit.ly/496keA7

@GEICO your such a broken company that you still charge to a credit card without checking that the date is valid. Wich is utterly predatory and should be illegal @CFPB