Marvell Technology

We are thrilled to announce that Matt Murphy, Chairman and CEO at @MarvellTech, will kick off Day 2 at The Six Five Summit: AI Unleashed 2026! 100% Virtual & Free. August 25-27. Register today: sixfivemedia.com/summit

Marvell®Teralynx® T100, the new 3nm 102.4T data center switch ASIC, was architected from the ground up for the AI challenge. Through a unique design and feature set that reduces power consumption and complexity, Teralynx T100 delivers the industry’s lowest latency for AI training and inference workloads. Ashwin Gopalan shares more about this industry first: mrvl.co/4ykYGMt

Marvell will have an active presence at the 63rd Design Automation Conference, with nine presentations spanning some of the most consequential challenges in advanced semiconductor design. Topics include scalable verification for 3D chiplet-based designs, physical signoff for 3DIC systems, thermal and IR analysis of stacked packages, fault tolerance and timing at the design edge, emulation and prototyping with FPGA solutions, and the next decade of semiconductor transformation across industry, academia, and government. @DACconference is the world's premier forum for electronic design and automation, drawing more than 6,000 engineers, architects, researchers, and executives. Marvell's participation reflects the depth of engineering expertise the company brings to advancing AI data center infrastructure. Learn more: mrvl.co/3SW8rRf

The global semiconductor market is booming, and the demand for engineering talent has never been greater. Marvell is investing in that pipeline directly. Scholarship programs now running in Vietnam and India reflect a deliberate commitment to developing the next generation of semiconductor engineers. The Vietnam Excellence Scholarship has supported 70 students with $80,000 USD since 2023, with 43% of recipients going on to intern at Marvell. This year, the program expanded to India with the launch of MSTEM, the Marvell Scholarship for Technical and Engineering Merit, which drew more than 7,000 applications from students at over 70 colleges. 100 scholars were selected, including 50% women and 20% first-generation winners. Beyond financial support, recipients receive mentoring to support their long-term career development across the semiconductor value chain. Learn more about Marvell's investment in emerging talent: mrvl.co/4yjqJfc

Scaling AI isn’t just a performance challenge. It’s a power and density problem. Inside the rack, connections outnumber those between racks by 10×, pushing traditional optical approaches beyond their limits. That’s why the industry is moving to co-packaged optics (CPO). At COMPUTEX 2026, Marvell Chairman and Chief Executive Officer Matt Murphy showcased a Marvell 100Tbps Teralynx switch and a next-generation CPO-based switch. Purpose-built to deliver the bandwidth, efficiency, and density required for AI at scale. See the video: mrvl.co/4vZLsDq

SerDes accounts for more than half of a switch chip. As Marvell Vice President of Cloud AI Data Center Switch Marketing Rajagopal Krishnaswamy puts it: "If SerDes does not work, nothing else matters." In an interview with DIGITIMES, Krishnaswamy details the technical challenges behind the Teralynx T100 and what comes next. The move from 100G to 200G SerDes represented a significant leap in signal integrity complexity. The next step is 400G, with development already underway across multiple process nodes, and research extending toward 800G and above. Advanced packaging is the other frontier. With single-chip designs approaching their physical limits, Marvell is preparing for more complex heterogeneous integration architectures that push beyond what a single mask can accommodate. Read more (free with account): mrvl.co/44U8S0U

Marvell has been named to both @usnews Best Companies to Work For and @TIME's America's Best Companies lists for 2026. The U.S. News recognition, which evaluates pay, work-life balance, stability, professional development and more, awarded Marvell a score of 29 out of 30. Marvell earned recognition across multiple categories including Manufacturing, Internships and Overall. TIME's inaugural America's Best Companies list assessed employee satisfaction, financial performance and sustainability transparency across the top 1,000 corporations nationally. For engineers and technologists looking to work on some of the most consequential problems in AI infrastructure, Marvell offers the scale, the technology, and the environment to do it. Learn more: mrvl.co/3T78p91

As AI clusters scale to tens of thousands of GPUs, Ethernet is no longer just a connectivity layer. It becomes a tightly coupled component of the compute system, where a single dropped packet can stall multiple GPUs and degrade overall utilization. Marvell and @Keysight demonstrated how the Marvell Teralynx switch fabric supports emerging Ultra Ethernet Consortium capabilities designed specifically for AI workloads: packet trimming, which preserves forward progress during congestion rather than triggering widespread retransmissions; Auto Load Balancing, which dynamically steers traffic away from congested links at line rate; and Ultra Ethernet Transport, which provides the framework within which both operate. Senior Engineer Vikram Dattatri details the technology and what rigorous system-level validation under realistic AI workload conditions demonstrates about its performance at scale. Learn more: mrvl.co/4yr2mMW

Doubling bandwidth cuts copper transmission distance in half. When we move to 400G, we can no longer fully connect a rack with copper. The copper wall is moving. Each time the wall moves one step, the number of connections goes up by at least an order of magnitude. This is creating an explosion in demand for the optical industry. So the optical supply chain needs to scale up massively. In this COMPUTEX 2026 keynote clip, Marvell Chairman and Chief Executive Officer Matt Murphy explains the physics and what comes next. Watch the full keynote: mrvl.co/4eWEw2t

Most CXL memory controllers expand capacity. Marvell Structera devices also compress it. The Compression-Decompression Block built into every Structera CXL device is dedicated silicon, operating at full memory bandwidth, that transparently compresses data on write and decompresses on read with no host CPU involvement and no application changes required. It is the first inline hardware memory compression solution in the industry to adhere to Open Compute Project specifications. With DDR5 server memory prices up 300 to 400% since mid-2025 and AI workloads doubling their memory requirements every 18 months, the economics are significant. Director of Product Marketing Arifur Rahman breaks down how it works and what it means for the cost structure of CXL memory pools. Learn more: mrvl.co/4xOaJ4A

For the third consecutive year, @TIME has recognized Marvell as one of the World's Most Sustainable Companies. In the most recent ranking, Marvell advanced into the top 5% globally among more than 5,000 companies evaluated. The recognition reflects measurable progress across several areas: Scope 1 and Scope 2 emissions reduced by 86% from a FY22 baseline through 97% renewable electricity sourcing, a CDP Supplier Engagement Leader A-List designation, an MSCI ESG Rating of AA, and a commitment to reducing Scope 3 emissions from sold products by 55% per petabyte per second by FY30. Sustainability at Marvell is embedded in how the company operates, innovates, and grows, from responsible supply chains to energy-efficient product design. Learn more: mrvl.co/4gRoxVV

Marvell will present at IEEE International Test Conference India 2026, now in its 10th edition and one of the semiconductor industry's leading forums for design verification, test, and silicon debug. Senior Principal Engineer Sreekanth G Pai and Senior Engineer Raseena K A will present on mission-mode scan dump using IJTAG and TAP customization, addressing one of the more demanding challenges in modern SoC development: maintaining robust observability and debuggability during mission-mode operation at scale. As SoC complexity continues to grow, the ability to efficiently access internal silicon states with minimal design impact is becoming a critical capability. Their session offers practical insight into IJTAG-based architectures, scan data extraction, and verification strategies for advanced semiconductor designs. Learn more: mrvl.co/3QIwbHy

. @MarvellTech Structera: Driving CXL Hardware Optimization & AI Memory Efficiency - Consolidates dedicated hardware compression, @Arm-driven near-memory computing & low-latency CXL switching into unified fabric shorturl.at/pk96z @StevenDickens3 @xconn @stephensopko

The lineup for The Six Five Summit: AI Unleashed 2026 keeps getting better. Confirmed opening keynote conversations: Keynote: Marc Benioff (@salesforce ) Day 1: Sridhar Ramaswamy (@Snowflake ) Day 2: Matt Murphy (@MarvellTech ) Day 3: Gary Dickerson (@Applied4Tech ) Plus leaders from @Broadcom, @Dell, @googlecloud, @intel, @MicronTech, @Oracle, @SamsungSemiUS, @solidigm, @Veeam & many more. Aug. 25–27 100% Virtual & Free Register: sixfivemedia.com/summit

At COMPUTEX 2026, Marvell made the case for why co-packaged optics is emerging as the preferred path for in-rack connectivity at AI scale, where density and power constraints are becoming increasingly difficult to meet with conventional approaches.

At COMPUTEX 2026, the industry got its first look at the Marvell Teralynx T100: the industry's first 102.4 Tbps switch purpose-built for AI data centers, delivering up to 25% lower power than competitive solutions.

What defines AI infrastructure performance at scale? Compute matters. Memory matters. But when tens of thousands of processors operate as a single engine, one thing matters most: Connectivity. In this clip from the Marvell COMPUTEX 2026 keynote, Chairman and CEO Matt Murphy breaks it down. See the full keynote: mrvl.co/44zCqRe

Plasmonics has a history stretching back to Roman glassmaking and has found applications in drug discovery and sensor technology. Marvell researchers are now applying its principles to one of the most demanding problems in AI infrastructure: scaling optical bandwidth beyond the limits of conventional silicon photonics. The research, carried out over more than 15 years by the team at Polariton, now part of Marvell, and ETH Zurich, has produced plasmonic modulator prototypes measuring approximately 10 microns in length and operating at 1 THz. Those figures represent a 300x to 500x reduction in size and more than 10x improvement in speed compared to existing silicon photonics devices, without requiring a departure from established foundry processes. Claudia Hoessbacher and Wolfgang Heni detail where the research stands and what it could mean for the next generation of co-packaged optical interconnects and scale-across networks: mrvl.co/4gDu2Yf