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$INTC CEO 陈立武这几天在摩根大通科技闭门会上 对英特尔内部设立的雷霆新规，被圈子疯传 >> 第一条:想保住工作，就做到A0、B0 芯片设计完送去晶圆厂，第一炉出来的版本叫 A0 有 bug 大改重做一次叫 B0，再改就是 C0、D0 台积电、苹果、英伟达几乎都是 A0 一把过 英特尔过去十几年经常改到 C0、D0 才能量产 每多一版烧几千万美金、耽误半年 陈立武说一开始大家以为他在开玩笑 现在知道他是认真的了 >> 第二条:客户告诉我的事比你早,你就完蛋了 倾听客户需求，达到客户标准 不容忍瞒报误报，提高透明度 过去财务说了算，营销说了算，工程师排最后 英特尔工程师曾经是三等公民 但现在企业文化逐渐被重塑 > 奇葩小国要翻身，靠的是天降猛男 陈立武之于英特尔 就如同卡加梅之于卢旺达 其实看看陈立武上一份工作成绩单就很清楚了 >> Cadence Design Systems(2009-2021) 2009 年 1 月，他接手的 Cadence: 股价 $5.50，从 2001 年峰值跌了 90% 营收从 $970M 缩到 $642M 内部官僚僵化、专利诉讼缠身 12 年后他卸任时: 营收:$1B → 近 $3B 经营利润率:扩张到 35%+ 股价:+3,200%(32 倍) 把深陷泥潭的公司塑造成领头羊 他在 Cadence 用的就是同一套打法—— 砍冗余、重建文化、客户至上、CEO 亲自下沉 现在他在 Intel，做的是同样的事 业绩兑现是周期 但企业文化重建 才是真正的复苏希望 持续看好英特尔的发展

几年前， $NOK 是一家濒临倒闭的电信设备公司 移动设备时代的明日黄花 股价不到 5 美元 现在它悄然出现在三个高景气赛道的聚光灯下 > 无线通讯：与英伟达展开新的 AI-RAN 合作 > 光通讯：通过 Infinera 为超大规模光学基础设施提供支持 > 国防科技：加入 Anduril 的哨兵系统中

Breaking the "Memory Wall": Optical Interconnects Emerge in GPU–HBM Packaging As a solution to the "memory wall," one of the chronic challenges in AI semiconductors, the memory and packaging industries at home and abroad are weighing an approach that decouples the GPU and high-bandwidth memory (HBM) and packages them separately. The core idea is to move the HBM—until now mounted right next to the GPU—a certain distance away, and bridge the gap with light (optics), allowing several times more HBM to be installed than is possible today. On the 22nd, a researcher at a major domestic memory maker said, "We're currently struggling to expand HBM bandwidth and capacity, so we're discussing with customers a plan to overcome the GPU's shoreline limit through optical interconnects and mount more HBM." Shoreline refers to the length of the chip's perimeter. In today's AI computing environment, the key factor dragging down compute efficiency is the data transfer speed of memory chips. While GPU performance has grown by leaps and bounds with each generation, the speed at which memory stores and supplies data has failed to keep pace—creating a structural performance barrier, the memory wall. The arrival of HBM, with its wide data pathways, put out the immediate fire, but critics continue to point out that bandwidth and transfer speeds still fall short of handling the explosive growth in AI compute. Until now, the industry has focused on stacking HBM ever higher to increase memory capacity and bandwidth within a confined footprint. But as stack counts climbed past 12 and 16 layers toward 20 and beyond, process difficulty rose exponentially. The technology hit physical limits, including the growing difficulty of meeting fixed height specifications. Vertical stacking has reached an inflection point—so much so that the JEDEC standards body has relaxed its HBM height specifications. The bigger problem is that if stack counts can't be raised, the alternative is to add more HBM horizontally around the GPU—but that, too, is impossible. In the current 2.5D packaging structure, the GPU and HBM are mounted tightly together on a single substrate. Within this structure, the number of HBM units that can be placed is strictly limited by the finite length of the GPU chip's perimeter—its shoreline. Even when more HBM is desired, there is physically no room to place it, leaving the industry in a structural deadlock. The alternative now emerging across the semiconductor industry is to separate the GPU and HBM and package them independently. It overturns the conventional chip-design principle that components must sit close together to minimize data transfer time. Instead of keeping the two chips adjacent, the approach spaces them apart and links them with overwhelmingly fast optical signals to overcome the added physical distance. Placing the HBM slightly away from the GPU within the board frees the design from the GPU's shoreline constraint. With the spatial limitation gone, far more HBM can be spread out laterally and packed into the board—several times more than today—without having to push stack heights to extremes. This means the total memory capacity and data bandwidth of the AI accelerator system would expand dramatically, on a scale incomparable to current systems. "Discussing Placing HBM Beneath the GPU"… Form Factor Could Change The industry is now producing a range of architectural design proposals over where exactly to place the HBM within the GPU board. The same memory researcher said, "Options under discussion range from broadly utilizing the space immediately around the GPU to isolating the HBM beneath the GPU board." He added, "In the latter case—isolating it beneath the GPU board—the motherboard would have to be extended lengthwise, so we're discussing even an overall form-factor change with the GPU maker." Specifically, the HBM might surround the GPU from several centimeters away, or a separate HBM zone might be created in the center of the board. "We're keeping every possibility open as we discuss the optimal layout," he said. "Nothing has been confirmed as an official roadmap yet, but as part of preliminary research toward next-generation AI accelerators, we're in talks with our partners." The outsourced semiconductor assembly and test (OSAT) industry is also watching this trend closely. An executive at a global OSAT firm said, "Optical interconnects are a clear trajectory. The only question is timing," predicting that "rack-to-rack and server-to-server links will go optical first, and then chip-to-chip connections within the board will follow." He added, "The larger units will be connected by light first, but optical research is moving so fast that it may not be that far off." Technically, the optical-interconnect technology linking GPU and HBM shares the same underlying principle as the technology connecting server to server inside a data center. The difference is the high technical barrier of shrinking optical-conversion technology—once used for communication between large pieces of equipment—down to the microscopic scale of a single board and chipset. An executive at a domestic developer of co-packaged optics (CPO) components explained, "As HBM stack heights approach their limit, the industry is discussing spreading the memory out laterally to maximize how much can physically be mounted." He added, "The principle is the same as conventional data-center optical interconnects, but HBM optical links that have to operate within a confined board space require optical components to be miniaturized to far smaller sizes and far higher integration density—so the technical difficulty is greater."

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最暴力快速布局量子领域的方式 以及如何买目前币圈大多币股券商还没上架的量子ETF 最近量子类股的议题慢慢比较多人在注意了 但目前很多币股团队都还没上架 如果大家有需求也可以先收藏这份清单 比如目前如果大家不知道买+啥可以买的量子etf QTUM（Defiance Quantum ETF）以及最新上市的 INFQ（Infleqtion Inc.） 就一直没有被大多团队上架 不过底下也会放解决方式 这里先好好介绍目前主线可以看的板块跟类型 一、 纯玩量子硬体股（高 Beta、高爆发力，适合激进型投资人） IONQ（IonQ Inc.） 技术路线： 离子阱（Trapped-ion） 最新动态： 目前无可争议的纯玩板块龙头。2026 年最新一季财报营收超出预期 30% 且首度转亏为盈，股价与市值双双迎来历史性转折。 特色： 与 AWS、Azure、Google Cloud 深度整合，商业化进程最快，是分析师最看好的指标股。 INFQ（Infleqtion Inc.） 技术路线： 中性原子（Neutral-atom）及量子感测 最新动态： 2026 年量子板块的焦点生力军。近期刚开源了关键的资源估算工具，并创下双原子纠缠闸保真度 0.975 的世界纪录。 特色： 深耕政府合约与感测运算，市值与股价处于早期高波动阶段，适合高风险偏好者。 QBTS（D-Wave Quantum Inc.） 技术路线： 量子退火（Quantum Annealing） 最新动态： 第一季订单额创下年增近 20 倍的纪录，近期透过收购开始将触角延伸至通用闸模型。 特色： 专精于物流与金融的最佳化问题，极度契合当下大型 AI 模型的训练与底层基础设施需求。 RGTI（Rigetti Computing） 技术路线： 超导（Superconducting） 最新动态： 正式在云端平台推出 108 量子位元系统。 特色： 拥有自家晶圆厂（Fab-1），技术推展稳健，是超导路线分散风险的第二梯队首选。 二、 量子安全与后量子加密（PQC，未来网路安全的硬底子需求） ARQQ（Arqit Quantum） 核心技术： 对称金钥协议（QuantumCloud 平台） 特色： 提供卫星与地面端的防破解加密解决方案。虽然市值规模小（约 2 亿美元），但 2026 年上半年营收展现极快的爆发力。 LAES（SEALSQ Corp） 核心技术： 后量子安全微控制器、安全半导体 特色： 将防护直接做进晶片根基，主打物联网（IoT）、汽车与工业设备的硬体防护，属概念独特的硬体安全股。