ultraembedded

I think I've built myself an HD (720p50) video player out of an #FPGA, #RISCV, #MJPEG and 27,000 lines of Verilog! Going from 800x600 -> 1280x720 just worked with 10 more MHz! I actually plan to sit down and watch a movie on this one evening! github.com/ultraembedded/…

@TheRetroHQ No, but I think @wren6991 had a RISCV core with debug/OCD support

@ultraembedded Hi! I’ve been looking through your RISCV and IP implementations, looks awesome! One question, as I’m still new to this stuff, do the debug bridges support OCD code debugging?

@wren6991 Maybe, one day!

@ultraembedded Oh I missed that this was in the context of your out-of-order completion in-order dispatch machine! Are you planning a full OoO?

Looking at implementing RISC-V atomic memory operations on top of AHB5 exclusives and hoo boy *slaps top of instruction* this bad boy can generate exceptions at so many different points in its execution

@wren6991 I treat them as a pipeline flush/fence and hold a global pipeline lock blocking new issue until they complete. Simplifies things a bit, but makes them slower.

@ultraembedded All of this to get what are effectively microcoded loops of the lr/sc instructions (if you are building on top of a lr/sc-like bus primitive like AHB5 exclusives). It's pretty silly tbh

@wren6991 I put another ALU in the LSU just for the AMO ops. It’s quite an annoying extension to implement, esp when mixed with an MMU, precise faults, etc.

Seems like "we have two easily composable instructions that perform one memory access each and let you implement arbitrary atomic read-modify-writes" would be the essence of RISC

@jonmasters @Arm Unmistakable reminder of a UK 80’s class room there. I seem to remember more ribbon cables being involved though. I owe a lot to my Acorn Electron 😀

The BBC Micro turned 40 this week and I turn 40 next week. If you were a kid in the UK in the 1980s, you grew up with the beeb. It was the platform you first learned to program on, and in my case led to a life long love of Acorn and @Arm

I couldn’t resist - just ordered a zynq 7020 and another ArtyA7 😀

@GregDavill Are you doing something with HDMI and USB2 by chance ?!

Pretty neat how flexible the ECP5 PPLs are, especially when you have 4, and can afford to cascade one into the next. Generating 74.25MHz / 371.25MHz / 60MHz all from a 30MHz input clock source.

@arjenroodselaar @GregDavill @PaulStoffregen Implementing the PCIe link is definitely non-trivial, with the ‘reward’ for all that effort being a single supplier proprietary protocol Ethernet PHY...

@GregDavill @PaulStoffregen The PCIe link itself is not too bad, but you may need to pick apart/RE the protocol Intel used on top of PCIe between their MAC and PHY. And then glue that to your existing MAC. No idea if this is documented somewhere but it may be the reason these PHYs are available :)

I don't need another project... But, I see that PCIe based ethernet PHYs are much more available than RGMII ones, and a tad cheaper. On an FPGA target, that has PCIe capable serdes. I'm curious how much effort is it to implement enough PCIe spec to use these in place of RGMII.

@tom_verbeure @bitsbytesgates I like it, a lot!

@bitsbytesgates I like it!

Question: you are simulating a RISC-V CPU that is running a C program. You are recording a VCD (or FST) trace. How do you correlate between the instruction address in the waveform and the line of C code?

@azonenberg @GregDavill I think I used sigrok when I was doing SD/MMC gateware. But I’d like to try glscopeclient someday.

@GregDavill FYI... glscopeclient has decodes for SD and eMMC command and data buses. Not sure if you've got a supported instrument yet, but if not we should fix that...

🎵 Hello darkness my old friend... 🎵

@mntmn These printfs look sort of familiar! It’s a ULPI setup isn’t it? If you DM me some more details / source versions used, I might be able to take a look tomorrow night.

@fontamsoc @enjoy_digital 16KB per way (32KB total). Yeah - I was planning to switch to LiteEth soon.

@ultraembedded Is it 32KB per way for a total of 64KB ? You could consider LiteEth by @enjoy_digital . I have been planning to use it for sometime now: #issuecomment-876570636" target="_blank" rel="nofollow noopener">github.com/enjoy-digital/…

Running iperf on Linux on my RV32IMA RISC-V CPU core. 13Mbit/s TCP perf is not impressive. Investigating why. Hmm.. 950K instruction cache refills per second causing the CPU to stall 35% of the time! Need more size/ways/levels, or maybe I could implement compressed ISA extension!

@mntmn I used the USB host core in another project with a ULPI Phy: github.com/ultraembedded/… In case this helps with connectivity issues, etc.

@mntmn Nice!

@MoonbaseOtago Yes, and Verilator is indispensable for this kind of stuff for speed reasons. I found snapshots (saved from a c model, restored in RTL sim) really useful to reduce the Linux boot debug time too. I’d be interested to hear about your design flow for something meaty like your CPU.

@ultraembedded Thanks - it's taken ~9 months - the 100 millions of instructions is really the great short term goal - when I last built CPUs (20 years ago) we didn't have the option of building something this fast - we had to get to this point on a verilog simulator

The time has come the walrus said ..... as some of you know I've been working on a very high end RISC-V implementation, now that it's booting Linux it's time to take off the covers and show it to the world. Here's a boot log: github.com/MoonbaseOtago/… 1/

@mntmn Nice. What frequency is the CPU running at?

@splinedrive @sylefeb Nice!

@ultraembedded @sylefeb It works niw I took your c code and modified it to generate a verilog rom table to initialize the it6613 via i2c without softcpu. Funny to have i2c with a rom table :) github.com/splinedrive/ha…

Oh, a new #fpga board!! (#ECPIX5 by @LambdaConcept with a 85F ECP5 by @latticesemi) Time for a new #Silice framework! This was the perfect opportunity to start a tutorial on adding new board: github.com/sylefeb/Silice…, work in progress)