william

@yacineMTB github.com/fontamsoc/rvpu

something deep inside my soul is telling me that i need to do it

i need to get into FGPAs. I don't know why, but I must

My implementation is an update based cache coherence protocol resembling the Dragon Protocol. The data-caches of each core are daisy-chained in a circle using valid-ready handshakes/connections through which the coherency traffic circulate.

You need cache coherency if you have more than one CPU, you want each CPU to use data cache, and you do not want to do manual data cache maintenance (ie: invalidate , writeback) to achieve coherency when accessing data shared by more than one CPU.

For the past 6 months, I have been working on cache-coherency.

In contrast, without data-cache, there are a lot more stalls, as each core struggles to keep a peak execution of an instructions every clock cycles.

16 cores simulation with data-cache showing the pc value of each CPU while running CoreMark. For the most part, each core is able to execute an instruction every clock cycles.

I have promising simulation showing 50.2 Coremark/MHz using 16 cores or 3.1 Coremark/MHz/Core. With single core at 3.5 Coremark/MHz, performance increases almost linearly from 1 to 16 cores. I am still working to make all tests pass to make a release.

@splinedrive @samsoniuk Hm... IMHO dividing by cores gives you the performance you would get if you use only 1 core out of the multi-cores available. However we mostly want the performance with all cores involved in the computation.

Raw CoreMark is marketing. CoreMark/MHz/Core is the truth. @samsoniuk CoreMark / MHz / Core Teensy 4.0 (600MHz,1C) 3.86 Metro M4 (200MHz,1C) 2.68 RP2350 DC (276MHz OC,2C) 2.60 RP2350 DC (200MHz OC,2C) 2.60 Metro M4 (180MHz,1C) 2.55 Teensy 3.6 (180MHz,1C) 2.45 Teensy 3.2 (72MHz,1C) 2.34 Teensy 3.2 (96MHz OC,1C) 2.27 Teensy 3.5 (120MHz,1C) 2.21 RP2350 DC (150MHz,2C) 2.00 Metro M4 (120MHz,1C) 1.79 Arduino Zero (48MHz,1C) 1.18 Arduino Due (84MHz,1C) 1.13 ESP32 (240MHz,2C) 0.73 Arduino Mega (16MHz,1C) 0.44 Arduino Nano Every (20MHz,1C) 0.41

@splinedrive I am revisiting which SDRAM controller to use; I have successfully used @ultraembedded SDRAM controller at: github.com/ultraembedded/… How does your SDRAM controller compare ?

This release falls short of what I wished to deliver; ie: multi-core data-cache-coherence, bare-metal gdb support. Nonetheless, this release has improved performance, with single-core CoreMark/MHz now reaching 3.5 from 2.8.

Release 20260102 github.com/fontamsoc/rvpu…

@splinedrive @ATaylorFPGA @samsoniuk Thanks ! Using the new Vivado IDE unlock option for dark theme.

@fontamsoc @ATaylorFPGA @samsoniuk Try

VIVADO 2025.2

@splinedrive @ATaylorFPGA @samsoniuk I installed Vivado 2025.2, but I am only seeing the "Light Theme"; how do I get dark mode ?

What the hell! Native dark mode, a stylish new Windows layout—look how nice my RTL view of the Linux KianV SoC looks. @ATaylorFPGA @samsoniuk

SystemVerilog is now used from this release going forward.

Release 20251021 github.com/fontamsoc/rvpu…

Release 20250930 github.com/fontamsoc/rvpu…

I am using the Lite version of TrafficMonitor to show CPU usage and other info on the taskbar without opening Task Manager.

@splinedrive I wish you would look into adding Baremetal RTOS capability using my _OS (underLineOS) approach (ie: in LibC), that is in my opinion simpler than FreeRTOS or Zephyr. Most Baremetal projects are just looking to use multi-threading along with sw-timer, mutex, semaphore and fifo.

Micropython on my own KianV - ASIC :)

Release 20250918 github.com/fontamsoc/rvpu…

@enjoy_digital Is there a guide on how to use LiteScope standalone in a Verilog design ?