iFred

Miles Davis, Kind of Blue [1959] Columbia All Blues Miles Davis – trumpet Julian "Cannonball" Adderley – alto sax John Coltrane – tenor sax Bill Evans – piano Paul Chambers – double bass Jimmy Cobb – drums

While we await for the deal, I think we can already highlight a few oil lessons: 1) Although we don’t yet understand how, China can reduce oil imports massively (>5m b/d cut) 2) Saudi/UAE bypass pipelines work 3) OECD nations can release their SPR at flow rates of >2.5m b/d

Samsung Electronics Achieves World's First "900-Layer V-NAND"… Countdown to the 1,000-Layer Era Samsung Electronics has become the world's first to successfully implement a prototype of 900-layer-class V-NAND technology, taking another step toward the era of "1,000-layer NAND." Amid intensifying layer-count competition with rivals, the achievement is being seen as Samsung securing a decisive technological lead in a single leap. According to the semiconductor industry on the 25th, Samsung recently realized an integrated 900-layer-class V-NAND system using "Cell Multi Bonding (CMB)" technology, which joins two 450-layer cell wafers into one. NAND flash, which stores data, is a core component in AI servers, smartphones, and data center storage (SSDs). Much like stacking floors in an apartment building, the higher the layer count, the more capacity can be packed into a limited chip footprint, allowing more data to be stored while maximizing power efficiency. It is regarded as a key technology for winning dominance in the AI server and on-device AI markets, where high-capacity, high-efficiency components are essential. In the current mass-production market, SK hynix holds the highest layer count with its 321-layer 4D NAND. However, Samsung—while preparing for mass production of its 10th-generation V-NAND (V10, 400+ layers) this year—has at the same time vaulted to the 900-layer mark at the research stage, positioning itself advantageously in the next-generation NAND market. Regarding these research results, Samsung stated that "normal cell operation characteristics were verified," emphasizing that this goes beyond mere theoretical stacking to demonstrate a level of capability that actually functions. Since commercializing 3D V-NAND for the first time in the world in 2013, Samsung has continuously evolved its processes to overcome stacking limits. In the past, it used a "single-stack" method of drilling and stacking fine holes in a single pass, but as layer counts rose, it ran into physical limitations such as wafer warpage and alignment errors. In implementing the 900-layer device, Samsung resolved wafer warpage—the biggest obstacle—by adopting an advanced upper chuck design. Misalignment errors that occur during bonding were overcome with its proprietary "new overlay correction" technology. Newly introduced bitline (BL) and wordline (WL) structures also delivered meaningful gains, simultaneously reducing power consumption and chip size. Globally, China—led by Yangtze Memory (YMTC)—is chasing Korean firms at the threshold of 300-layer-class NAND mass production. With government support and the localization of equipment, it is pursuing capacity expansion and technological advancement at the same time. If YMTC succeeds in mass-producing 300-plus layers within the year, price competition could intensify and pressure Korean firms' profitability. For this reason, Samsung's 900-layer achievement is highly regarded as a strategic move to build a technological barrier over the medium-to-long term. An industry official said, "900-layer NAND technology is not simply three times 300 layers—it is a technology that changes the paradigm of the stacking process," adding, "It sends global customers the message that Samsung remains the technology leader, and it will have the effect of limiting Chinese firms' volume and price offensive."

What’s the name of this band?

Simple explanation: It's an advanced variant of 3D stacking with smart wire placement and shorter critical path wires

HUAWEI has presented the Tau (τ) Scaling Law, a new principle for guiding the future development of the semiconductor industry. By 2031, HUAWEI's high-end chips based on this law are expected to feature a transistor density that is equivalent to 14 Å (1.4 nm) processes.

Tbh, I think covering the capacity by expanding the CPU's DRAM and CXL is a more realistic solution than HBF. The more I look at HBF and NAND, the more my skepticism is reinforced because their fundamental origins are different from DRAM...

The report claiming that NVIDIA is using HBF is fake news. I’m extremely disappointed in TrendForce. For a reputable firm like TrendForce to cite a The Elec article that was based on one professor’s opinion, and then reinterpret it as if The Elec reported that NVIDIA is trying to use HBF, is simply unacceptable. This is not true at all. NVIDIA is looking to use high-reliability, high-speed NAND, such as 200M IOPS NAND, for GIDS. It is not considering HBF.