hari_haran@HariAyapps
We built the best chip design engine in the world!! 🥳🥳
@archgen_ is currently ranked #1 on the @WeAreHRT / Partcl Macro Placement Challenge 2026 leaderboard.
Macro placement is one of the hardest problems in physical design.
It involves placing large fixed-size blocks such as SRAMs, IPs, and analog macros on a chip floorplan while balancing, wirelength, density, congestion, routability, timing and constraints.
After months of research and iteration our submission reached a verified rank-1 with an average proxy cost of 0.9507 across the IBM benchmark suite.
@naveen_venk and @JishnuMada86596 burned the midnight oil to build an optimization flow that combined fast local repair, multi-start search, congestion-aware ranking, GPU-accelerated candidate generation and strict legality checks to reach the top spot. (detailed blog in the comments)
Grateful to Madhusudan S, Abhishek Lal, and Anant Gulati for their valuable suggestions and inputs to help us overcome issues in EDA algorithms, traditional macro placement algorithms and GPU optimisation.
If you are working on physical design and want to understand how AI, self learning agents, loops, and GPU-accelerated optimisation can improve your flows please feel to reach out to us.
Thank you @Willschips, Vamshi Balanaga and the Partcl team for organising this competition.
#PhysicalDesign #EDA #ChipDesign #VLSI #AIforEDA #Semiconductors #Placement #ArchGen #HardwareDesign