Andrew Zonenberg @[email protected]

I've received a lot of questions about my various open source projects, status of them, etc. Made a public google doc with everything: #gid=0" target="_blank" rel="nofollow noopener">docs.google.com/spreadsheets/d…

@BreakingTaps That's the biggest comb drive I've ever seen...

Not entirely functional yet, but sure does look neat! Working on an electrostatic demonstrator. 🙂 Flexure ended up a bit too floppy (center mass is heavier than expected), need to rework it to be a little stiffer. Still.... getting closer!

@Fraser_RG @funranium Yep this was my thought too. Also useful after other kinds of hazmat incident.

CHOOSE YOUR OWN RADIATION ADVENTURE You're handed an extremely large sum of money to DO SOMETHING about the terrorists and radiation and mumblemumble it wasn't really worth paying attention because they didn't know what they wanted, which seems like the best investment?

@tom_verbeure @EndoOleg It's very common to abuse FPGA LVDS inputs as comparators. I made a 100baseTX Ethernet PHY on an FPGA using two LVDS inputs and three resistors as a 1.5 bit 500 Msps flash ADC.

@EndoOleg I think you're on to something. Googling for "FPGA LVDS as comparator" gives a bunch of links, though it's not clear if works over a large a voltage range as required for the DSLogic (0V to 2.5V). It's also makes it possible to use the LVDS deserializer for high speed sampling.

Riddle of the day: I've been looking at the input circuit of a DSLogic U3Pro16 logic analyzer. They claim 250kOhm input impedance. You can specify a voltage threshold from 0V to 5V in steps of 0.1V. I've ohm'ed out the following schematic. See ALT for commentary.

@Astro_Chuck @RFgeekPC Yeah the large wavelength is annoying. I've been thinking of building a C-band (5.8 GHz ISM/amateur band, giving me the option of operating under either set of regs) PESA for a while. Original dream was AESA but those are $$$$$ :(

@RFgeekPC 915 MHz, not the best frequency I'm sure but I know what permissions I have in that band and components are cheap.

My FMCW radar is getting ready for a smoke test! I'm going to try doing ground tracking of my rockets. This math is really challenging for me but I might pull it off!

@TracketPacer @kwiat_riot_1 @petergjones @EthernetAllianc (also I'm not really active on here except replying when I'm specifically requested, all of my regular posts are on Mastodon now)

@TracketPacer @kwiat_riot_1 @petergjones @EthernetAllianc Triggering is also problematic unless you can probe TX_EN/RX_EN of one of the endpoint PHYs, because the scrambling means you have continuous toggles even when there's no packets in flight. Assuming you want to decode vs just seeing an eye pattern for SI work.

First time hooking up my scope to ethernet. Is this the correct waveform for 100baseT? I am using a breadboard setup from the pic, no diff probe. Calling @TracketPacer @petergjones @EthernetAllianc

@fluxotronlabs @pepijndevos As long as you don't mind 2-3 WFM/s over SCPI at best, dropping to <1 at deeper memory, sure. I like scopes that can push Gbps of waveform data to a PC but the list is short.

@azonenberg @pepijndevos +1 for the sds2000x, great usability for daily driver on the bench

@azonenberg what's your current rec for entry level scopes? Iirc somewhere between rigol and some usb scope?

@mtaht @networkservice @ioshints The next gen design (LATENTORANGE) is going to use a much larger FPGA with more SERDES lanes (probably Xilinx Kintex UltraScale/Ultrascale+). LATENTRED is trying to cram 24x 1G baseT + 1-2x 10G SFP+ uplink into an XC7K160T.

@mtaht @networkservice @ioshints I mean the datapath is all FPGA so you might have to do some tweaking, but if there's enough gates free I don't see why not. That said, the initial (LATENTRED) switch design is using a fairly small FPGA so I'm not sure how much fanciness you could fit in it.

Is dynamic MAC learning (= updating MAC table) done in hardware or are the packets from unknown sources punted to the CPU? Any pointers to real-life information would be highly appreciated. Thank you!

@ioshints @networkservice I've mostly moved to Not-Twitter (see username on my profile) and am posting a fair bit about the project over there. Only checking in here every once in a while to point people at what I'm doing there. Current status: debugging power supply issues causing SGMII BER problems.

@azonenberg @networkservice Thanks for the pointer! Next step: trying to figure out what you’re doing :)

@networkservice @ioshints I can't speak to commercial switch chipsets, but #L34" target="_blank" rel="nofollow noopener">github.com/azonenberg/lat…

@networkservice @ioshints The MAC address table in my (WIP) open hardware switch manages all learning and lookups in gateware. No CPU interaction is required whatsoever during normal operation; all it does is translate ASCII text CLI commands to register writes when you change VLAN settings etc.

@Ascii211 But did you reflash drive firmware too and verify with a JTAG/SPI dump? :P Side note, this is (one of) the reason I run all of my browsers in VMs that I can trivially blow away if there's a problem.

*sigh* incident response is not one of my favored things to do.

Took the nuclear option on a computer that got hit with a browser hijack from a bad click, wiped and zeroized the drive, then reflashed BIOS and IME, now installing a fresh copy of windows.

@TracketPacer Lab rack *of FPGAs*?

lab rack or FPGA or keyboard lab rack or FPGA or keyboard lab rack or FPGA or keyboard TOO MANY INTERESTING THINGS

@FizzOtter Most of the folks I interact with have been there largely, or exclusively, for months now. I'm barely on here anymore.

@tom_verbeure @splinedrive @MoonbaseOtago @samsoniuk @ATaylorFPGA @controlpaths So by using a BUFGCE on the PLL output, this is avoided. I only do this with clocks that are stably derived (i.e. coming from an oscillator) rather than something from a CDR that is expected to change speed or come/go at run time.

@tom_verbeure @splinedrive @MoonbaseOtago @samsoniuk @ATaylorFPGA @controlpaths This is important if you only use the FPGA POR to initialize registers and don't have an explicit RTL reset - you need to *never* give the logic a clock pulse that's too short once the POR clears (which happens way before the PLL locks).

Pro and Cons using asynchron resets in #fpga? @MoonbaseOtago @samsoniuk @furan @tom_verbeure @ATaylorFPGA @controlpaths ...