liam liu
70 posts







🏭 Bigger Packages, Bigger Warpage Problems AI chip packages scale toward 12x reticle size by 2028, up from 3–4x in 2023 on TSMC and Intel roadmaps. At that scale, warpage is the key constraint in panel-level packaging. TSMC's VisEra runs a CoPoS trial line this year; AMC, WaferChem, and Everlight Chemical are positioning for the warpage suppression market. Assess the materials and suppliers defining PLP yield 👉 buff.ly/Okkj8mW Explore Warpage Challenges in AI Chip Packaging 📖 buff.ly/35u7PN9 #TrendForce #SelectedTopics

Chip supply chain talk defaults to Taiwan. Intel runs an entire parallel chain that never touches the island. This is the life cycle of a single Xeon chip: Compute tiles in Ireland and Arizona. IO tiles in Israel and Arizona. EMIB advanced packaging in New Mexico. Assembly in Costa Rica. Test in Chengdu. Five countries, three continents, zero Taiwan.


A new era of PC. 25.0528, 121.5990















